Design and Analysis of CMOS Based DADDA Multiplier

Multiplier is an important circuit used in electronic industry especially in digital signal processing operations such as filtering, convolution and analysis of frequency. There are different types of algorithms used in multipliers to achieve better performance. Array multiplier and Wallace tree multiplier are such types of multipliers constructed by using CMOS logic styles such as Swing Restored complementary Pass-transistor Logic (SR-CPL) and Dual Pass-Transistor (DPL). SR-CPL is constructed by using n-MOS transistor that is derived from Complementary Pass Logic (CPL) logic which is traditionally applied to the arithmetic building block and it offers high speed. DPL is constructed by using both n-MOS and p-MOS which has more number of transistors compared to that of SR-CPL. But high robustness is achieved through DPL. However Wallace multiplier offers higher power consumption. Hence, DADDA multiplier is designed by using ripple carry and carry save adder method with the above mentioned two logic styles. The simulation is done by using TANNER EDA tool.